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| flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copi ed customer support: page 1 of 74 1 - 888 - 824 - 4184 FIDO1100 ? data sheet 32 - bit real - time communications controller
flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copi ed customer support: page 2 of 74 1 - 888 - 824 - 4184 copyright 2013 by innovasic, inc. published by innovasic, inc. 5635 jefferson st. ne, suite a, albuquerque, new mexico 87109 usa fido ? , FIDO1100 ? , and spider are trademarks of innovasic , inc. i 2 c? bus is a trademark of philips electronics n.v. motorola is a registered trademark of motorola, inc. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 74 1 - 888 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 5 list of tables ................................ ................................ ................................ ................................ ... 6 1. overview ................................ ................................ ................................ ................................ . 7 2 . features ................................ ................................ ................................ ................................ ... 9 2.1 core cpu ................................ ................................ ................................ .................... 10 2.2 jtag ................................ ................................ ................................ ........................... 10 2.3 internal memory and memory management ................................ .............................. 11 2.4 external bus interface ................................ ................................ ................................ . 12 2.5 pmu/uic/cpu dma ................................ ................................ ................................ . 12 2.6 internal peripherals ................................ ................................ ................................ ..... 13 2.6.1 timer counter units (tcu) ................................ ................................ ........... 13 2.6.2 analog - to - digital converter (adc) ................................ ............................... 14 2.6.3 timers ................................ ................................ ................................ ............. 14 2.7 power control ................................ ................................ ................................ ............. 14 3. libraries and support tools ................................ ................................ ................................ . 15 4. packaging, pin descriptions, and physical dimensions ................................ ....................... 16 4.1 pqfp package ................................ ................................ ................................ ............. 17 4.1.1 pqfp pinout ................................ ................................ ................................ ... 17 4.1.2 pqfp physical dimensions ................................ ................................ ............ 24 4.2 bga 15 - by 15 - mm package ................................ ................................ ...................... 25 4.2.1 bga 15 - by 15 - mm pinout ................................ ................................ ............. 25 4.2.2 bga 15 - by 15 - mm physical package dimensions ................................ ....... 33 4.2.3 b ga 15 - by 15 - mm signal routing ................................ ............................... 34 4.3 power and ground signals ................................ ................................ .......................... 36 5. electrical characteristics ................................ ................................ ................................ ...... 38 6. thermal characteristics ................................ ................................ ................................ ........ 41 7. reset ................................ ................................ ................................ ................................ ..... 42 7.1 overview ................................ ................................ ................................ ..................... 42 7.2 signal considerations and reset timing ................................ ................................ .... 42 7.3 clock signals ................................ ................................ ................................ ............... 44 7.4 typical clock source impleme ntations ................................ ................................ ...... 44 7.4.1 normal or driven clock source ................................ ................................ ..... 44 7.4.2 using an external crystal ................................ ................................ ............... 44 7.5 off - chip component value ................................ ................................ ........................ 46 8. signals ................................ ................................ ................................ ................................ ... 47 8.1 external bus operation ................................ ................................ ............................... 47 8.1.1 overview ................................ ................................ ................................ ......... 47 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 74 1 - 888 - 824 - 4184 8.2 general setup and hold timing ................................ ................................ .................. 47 8.3 external bus timing ................................ ................................ ................................ ... 48 9. setup and hold timing ................................ ................................ ................................ ......... 49 9.1.1 external bus timing for a 32 - bit transfer (without rdy_n) ...................... 51 9.1.2 external bus timing for a 32 - bit transfer (with rdy_n) ........................... 52 9.1.3 external bus timing for 8 - bit/16 - bit transfer (without rdy_n) ................ 54 9.1.4 external bus timing for 8 - bit/16 - bit transfer (with rdy_n) ..................... 55 9.2 sdram timing ................................ ................................ ................................ .......... 56 9.2.1 sdram ca s timing ................................ ................................ ..................... 56 9.2.2 sdram row activation timing ................................ ................................ ... 57 9.2.3 sdram read operation timing ................................ ................................ ... 59 9.2.4 sdram read burst timing ................................ ................................ .......... 59 9.2.5 sdram write operation, write burst, write - to - write, and write - to - precharge timing ................................ ................................ ............................ 60 10. jtag ................................ ................................ ................................ ................................ ..... 64 10.1 jtag scan chain debug functionality ................................ ................................ ...... 65 11. ordering information ................................ ................................ ................................ ............ 67 12. errata ................................ ................................ ................................ ................................ ..... 68 12.1 summary ................................ ................................ ................................ ..................... 68 12.2 detail ................................ ................................ ................................ ........................... 68 13. revision history ................................ ................................ ................................ ................... 72 14. for additional information ................................ ................................ ................................ ... 74 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 74 1 - 888 - 824 - 4184 list of figures figure 1. block diagram for the FIDO1100 ................................ ................................ ...................... 8 figure 2. pqfp package diagram ................................ ................................ ................................ 17 figure 3. pqfp physical package dimensions ................................ ................................ ............. 24 figure 4. bga 15 - by 15 - mm package diagram ................................ ................................ ......... 26 figure 5. bga 15 - by 15 - mm phy sical package dimensions ................................ ...................... 33 figure 6. bga 15 - by 15 - mm signal routing ................................ ................................ .............. 35 figure 7. reset timing ................................ ................................ ................................ ................. 43 figure 8. extended reset timing ................................ ................................ ................................ . 43 figure 9. driven clock source ................................ ................................ ................................ ..... 45 figure 10. crystal o scillator third overtone off - chip components ................................ ......... 45 figure 11. crystal oscillator fundamental overtone off - chip components .............................. 45 figu re 12. propagation delay ................................ ................................ ................................ ....... 49 figure 13. setup time ................................ ................................ ................................ ................... 49 figure 14. hold time ................................ ................................ ................................ .................... 50 figure 15. recovery time ................................ ................................ ................................ ............ 50 figure 16. removal time ................................ ................................ ................................ ............. 50 figure 17. minimum pulse width ................................ ................................ ................................ 51 figure 18. external bus timing for a single, 32 - bit cycle (without rdy_n) ........................... 52 figure 19. external bus timing for a 32 - bit transfer (with rdy_n) ................................ ........ 53 figure 20. external bus timing for 8 - bit/16 - bit transfer (without rdy_n) ............................. 54 figure 21. external bus timing for 8 - bit/16 - bit tr ansfer (with rdy_n) ................................ .. 55 figure 22. sdram cas timing ................................ ................................ ................................ . 57 figure 23. specific row activation timing ................................ ................................ ................. 58 figure 24. meeting trcd (min) when 2 < trcd (min)/tck 3 ................................ ................ 58 figure 25. sdram read operation timing ................................ ................................ ................ 59 figure 26. sdram read burst timing ................................ ................................ ....................... 60 figure 27. sdram write operation timing ................................ ................................ ............... 61 figure 28. sdram write burst t iming ................................ ................................ ...................... 62 figure 29. sdram write - to - write timing ................................ ................................ ................. 62 figure 30. sdram write - to - precharge timing ................................ ................................ .......... 63 figure 31. jtag state machine ................................ ................................ ................................ ... 64 figure 32. jtag port register interface ................................ ................................ ...................... 65 figure 33. tim ing of jtag signals ................................ ................................ ............................. 65 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 74 1 - 888 - 824 - 4184 list of tables table 1. key features ................................ ................................ ................................ ..................... 7 table 2. test pin descriptions ................................ ................................ ................................ ...... 11 table 3. pqfp pin listing ................................ ................................ ................................ ............ 18 table 4. bga 15 - by 1 5 - mm package pin listing ................................ ................................ ....... 27 table 5. analog power and ground signals ................................ ................................ ................. 36 table 6. crystal oscillator power and ground signals ................................ ................................ 36 table 7. 2.5 vdc digital core power signals ................................ ................................ ............. 36 table 8. 3.3 vdc digital io power signals ................................ ................................ ................. 37 table 9. digital ground signals ................................ ................................ ................................ ... 37 table 10 . absolute maximum ratings ................................ ................................ ......................... 38 table 11 . esd and la tch - up characteristics ................................ ................................ ............... 38 table 12 . recommended operating conditions ................................ ................................ ........... 38 table 13 . dc characteristics ................................ ................................ ................................ ........ 39 table 14 . input impedance ................................ ................................ ................................ ............ 39 table 15 . ac characteristics of crystal oscillator ................................ ................................ ....... 39 t able 16 . analog - to - digital converter characteristics ................................ ................................ 40 table 17 . power consumption ................................ ................................ ................................ ...... 40 table 18 . thermal resistance character istics ................................ ................................ .............. 41 table 19 . hardware signals involved when asserting reset ................................ ...................... 42 table 20 . suggested off - chip component values ................................ ................................ ....... 46 table 21. debug scan chain commands supported by the jtag tap ................................ ...... 66 table 22. part numbers by package types ................................ ................................ .................. 67 table 23. summary of errata ................................ ................................ ................................ ........ 68 table 24. revision history ................................ ................................ ................................ ........... 72 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr i nted or copied customer support: page 7 of 74 1 - 888 - 824 - 4184 1. overview innovasic semiconductors FIDO1100 is the first product in the fido family of real - time communication controller s. the fido communication controller architecture is uniquely optimized for solving memory bottlenecks, and is designed from the ground up for deterministic processing. critical timing par ameters, such as context switching and interrupt latency, are precisely predictable for real - time tasks. the FIDO1100 also incorporates the universal i/o controller (uic ) that is configurable to support various communication protocols across multiple pla tforms. this flexibility relieves the designer of the task of searching product matrices to find the set of peripherals that most closely match the system interface needs. the s oftware p rofiling and i ntegrated d ebug e nvi r onment (spider ) has extensive re al - time code debug capabilities without the burden of code instrumentation (see table 1 ) . figure 1 illustrates the top - level blocks of the FIDO1100 architecture. table 1 . key features feature s benefit s programmable uic provides th e ability to customize peripherals to match user application. single chip can solve multiple end - product demands. reduces costs through optimized inventory management. five hardware contexts run s tight - control loops in separate c ontexts while rtos manages high level tasks in another context. provides con text isolation with robust time - and - space partitioning. low - jitter execution performs tasks at much lower clock rates (66mhz versus >200mhz), reducing power budget and simplifying board design. spider r ed uces system integration and debug time through in - system , what - if testing without code changes. red uces firmware development time thus cutting costs. up to 1mbyte of trace buffer. long - life - cycle support fulfills innovasics corporate policy of supporti ng products for the customers entire life - cycle, eliminating product obsolescence concerns. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 74 1 - 888 - 824 - 4184 figure 1 . block diagram for the FIDO1100 c o r e c p u e x e c u t i o n u n i t p r i o r i t y c o n t r o l c p u d m a t i m e r s p e r i p h e r a l m a n a g e m e n t u n i t a n d f r a m e b u f f e r s t i m e r c o u n t e r u n i t e x t e r n a l b u s i n t e r f a c e s d r a m c o n t r o l l e r r r e m a n d m p u s p i d e r ? d e b u g s r a m j t a g d e b u g 1 0 - b i t 8 - c h a n n e l a d c u i c _ 0 u i c _ 1 u i c _ 2 u i c _ 3 t 1 i n t 0 i n t 1 i c [ 3 : 0 ] t 0 i c [ 3 : 0 ] t 1 o c [ 3 : 0 ] t 0 o c [ 3 : 0 ] d [ 1 5 : 0 ] a [ 3 0 : 0 ] r w _ n c s [ 7 : 0 ] _ n h l d r e q _ n r d y _ n h l d g n t _ n o e _ n b e [ 1 : 0 ] _ n m e m c l k b a [ 1 : 0 ] r a s _ n c a s _ n c k e u i c 0 [ 1 7 : 0 ] t d i t c k t d o t m s v r h a n [ 7 : 0 ] v r l u i c 1 [ 1 7 : 0 ] u i c 2 [ 1 7 : 0 ] u i c 3 [ 1 7 : 0 ] d m a [ 1 : 0 ] _ a c k d m a [ 1 : 0 ] _ r e q i n t [ 7 : 0 ] c o n t e x t m a n a g e r flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 74 1 - 888 - 824 - 4184 2. features the FIDO1100 communication controller s features include: 32 - bit core cpu cisc arc hitecture optimized for real time cpu32+ (motorola? 68000) instruction - set compatible five hardware contexts, each with its own register set and interrupt vector table an 8 - or 16 - bit external bus interface with programmable chip selects 24 kbytes of high - speed internal user sram 32 kbytes of high - speed internal user - mappable relocatable rapid execution memory (rrem) a memory protection unit (mpu) an sdram controller flat, contiguous memory space n on - aligned memory access support d edicated peripheral manage ment unit (pmu) four universal i/o controllers (uics) capable of supporting the following protocols: C gpio C 10/100 ethernet with flexible mac address filtering schemes C eia - 232 C can C spi C i 2 c bus C smbus C hdlc two channels of full - featured direct memory access (dma) with deterministic arbitration two timer/counter units (tcu) a watchdog timer, system timer, and context timers flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 74 1 - 888 - 824 - 4184 jtag emulation and debug interface available in 208 - pin pqfp and bga 1 5 - by 15 - mm packag e s 3.3v operation with 5v - tolerant i/o industrial temperature grade software development supported by libraries and tools including uic firmware for various interface protocols and formats, as well as a customized gnu tool set. 2.1 core cpu t he FIDO1100 core is based on the cpu32 architecture, and is compatible with the cpu32 instruction set. the FIDO1100 incorporates five independent hardware contexts. while a ll contexts share the same execution unit, each of the five hardware contexts in t he FIDO1100 has its own register set , execution priority and exception vector table. from an applications view, t his unique feature of the fido 1100 allows it to operate as five independent machines in one : 32 - bit address and data paths on - chip 66 - mhz op eration instruction execution from external memory or fast internal memory. each hardware context has its own copy of: C eight 32 - bit user data registers (d0 - d7) C seven 32 - bit address registers (a0 - a6) C two 32 - bit stack pointers (a7 and a7') C one 32 - bit progra m counter C one 16 - bit status register (sr) C one 32 - bit vector base register (vbr) 2.2 jtag the FIDO1100 is fully compliant with the ieee 1149.1 test access port and boundary - scan architecture (see table 2 ) . the FIDO1100 architecture is equipped with the tap ( test access port) interface, tap controller, instruction register, instruction decoder, boundary - scan register, and by - pass register. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 74 1 - 888 - 824 - 4184 table 2 . test pin descriptions pin direction description tdo in test data output the tri - state t est data output changing on the falling edge of the tck input. this is actively driven only in the shift - dr and shift - ir controller states. tdi in test data input the test data input sampled on the rising edge of the tck input. tms in test mode select i nput the test mode select input used to sequence the tap controller state machine. if tms is a 1 for 5 clock cycles, it sends the tap controller into reset. if tms is 0, the tap controller goes to idle. tck in test clock input all jtag commands and seri al data are synchronized by this signal. the jtag interface is used for controlling the spider debug f e atures of the FIDO1100. breakpoints eight hardware context - aware breakpoints that can be chained to set up if/then triggering conditions. C hardware brea kpoints are enabled in software or over jtag watchpoints eight hardware watchpoints. trace follow program execution with trace buffers. C single address, single buffer , and circular buffer trace modes C trace buffer can be written anywhere in the address spac e or to a peripheral debug control hardware single - step and context status control. C access to all memory and registers that are accessible to software C byte, word, and long - word access in full - address mode or offset mode C invalid address access (keystroke er rors) over jtag will not kill the session C direct programming of flash on the evaluation board without target software support C built - in hardware support to halt contexts and execute single instructions without software C jtag access to registers, stack space, etc ., even if the processor is halted statistical profiling spider provides statistical software profiling to identify critical pieces of code . 2.3 internal memory and memory management user sram internal 24 - kbyte memory that can be used by applications for general purpose data needs or as trace buffers. relocatable rapid execution memory (rrem) internal 32 - kbyte memory that can be used as an instruction source for code that requires maximum execution speed. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 74 1 - 888 - 824 - 4184 memory protection unit (mpu) access - control method for 16 user - configurable blocks of internal or external memory on a context basis. a block of memory may be inaccessible, read only or read/write accessible to a selectable set of contexts. the mpu provides the space partitioning needed in deterministic, real - time systems. 2.4 external bus interface the interface to all external memory. it handles memory interface timing and arbitration of external bus requests. the external bus interfaces provide all address, data, and control line to implement either an 8 - or 16 - bit microcontroller system bus. address/data bus C 31 - bit address bus to access up to 2 gbytes of memory space C 8 - or 16 - bit data bus C zero - overhead endian conversion chip selects eight programmable chip selects with programmable size, data width, an d timing. sdram controller supports 8 - or 16 - bit data interfaces to sdram and provides the necessary control signals to interface to external sdram. the interface to the external sdram uses the 16 - bit - wide data bus and 13 bits of the address bus of the ex ternal bus interface. the dedicated clock signal for this interface (memclk) operates at the same frequency as the internal master clock. C operates at a maximum clock rate of 66 mhz C executes read, write, pre - charge, auto refresh, power down, and initialize sdram modes C fixed, 4 - word bursts to/from sdram interface C periodically issues auto refresh command to prevent sdram data loss external bus arbitration the FIDO1100 provides signals to allow it to operate in a multi - bus master environment. 2.5 pmu/uic/cpu dma the pmu, uic, and cpu dma work together as a fast data transport scheme that requires minimal core cpu overhead or intervention. peripheral management unit (pmu) a set of user - configurable buffers for data transmission and reception via the uics. universal input/output controller (uic) programmable protocol engine . flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 74 1 - 888 - 824 - 4184 the uic is a very flexible hardware solution designed to support numerous interface requirements. when working in concert with the on - board peripheral management unit (pmu) and on - board data buf fers, the operation of the interfaces requires little core processor intervention. this allows the processor to use its bus bandwidth for more important functions than managing data traffic. the uic design can support complex protocols such as ethernet o r gpio functions. four software - configurable uics each supports 10/100 ethernet, can, uart, spi, i 2 c, hdlc, or gpio functionality software libraries are provided for various interface protocols and formats user - programmable integrated 256 - location mac addr ess filter dedicated pmu offloads main cpu bus traffic large 1k 32 transmit buffer and 2k 32 receive buffers at a minimum, each uic can support 1 ethernet port (mii), 2 uarts, or 18 gpio cpu dma two independent channels of dma for data transfer 2.6 interna l peripherals the FIDO1100 incorporates the following set of internal peripherals: 2.6.1 timer counter units (tcu) two timer counter units (tcu) the FIDO1100 is equipped with two timer counter units. C four channels per timer; any channel can be either input capt ure or output compare. C input captures can be either rising or falling edge . C external signal clocking can be rising edge, falling edge, or both edges of input signal . C output compare can be assert high, assert low, or toggle mode . C underflow, overflow, input - capture, or output - compare conditions can trigger an interrupt . C timers can be programmed for auto - stop or auto - reload . C timer can generate an internal interrupt to wake up the processor from sleep mode . C timer periods in excess of 50 seconds are achievable . flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 74 1 - 888 - 824 - 4184 2.6.2 analog - to - digital converter (adc ) C 8 - channel, 10 - bit adc C maximum throughput rate of 200 kbps C high - and low - reference voltage pins ensure accuracy and temperature compensation C very low 5 - mw power consumption and includes a built - in power - down mode C single - or multiple - channel conversion scan modes C interrupt generated at the end of conversion is assigned a priority and a context C interrupts from the analog - to - digital converter can be disabled 2.6.3 timers system timer . C provides five periodic system timer interrupts. o 16 - bit counter with 16 - bit prescale allows a range of system timer interrupts from 80 ns to 50 seconds with a 66 - mhz system clock . o these interrupts can be assigned to the fast - context switching hardware providing a zero overhead system executive or the sy stem timer interrupts can simply produce a traditional vectored interrupt request to provide a system with basic timing needs . watchdog timer C 16 - bit counter with an 11 - bit prescaler context timers C each hardware context has a set of timing registers that c an track, specify, and limit execution time. 2.7 power control all i nternal peripherals can be put into a low - power consumption mode . flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 74 1 - 888 - 824 - 4184 3. libraries and support tools full library support uic libraries embedded communication stacks tcp/ip gpio sample programs cust omized gnu tool set eclipse ide sourcery g++ from code sourcery flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 74 1 - 888 - 824 - 4184 4. packaging , pin descriptions , and physical dimensions information on the packages and pin descriptions for the FIDO1100 communication controller pqfp and bga 15 - by 15 - mm package is provided i ndividually. refer to sections, figures, and tables for information on the device of interest. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 74 1 - 888 - 824 - 4184 4.1 pqfp package 4.1.1 pqfp pinout the pinout for the FIDO1100 communication controller pqfp package is as shown in figure 2 . the corresponding pinout is provided in t able 3 . figure 2 . pqfp package diagram r e s e t _ n r e s e t _ o u t _ n flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 74 1 - 888 - 824 - 4184 table 3 . pqfp pin listing pin signal name type description 1 an_7 input analog - to - digital converter input channel 7 2 an_6 input analog - to - digital converter input channel 6 3 an_5 input analog - to - digital converter input channel 5 4 an_4 input analog - to - digital converter input channel 4 5 an_3 input analog - to - digital converter input channel 3 6 an_2 input analog - to - digital converter input channel 2 7 an_1 input analog - to - digital converter input channel 1 8 an_0 input analog - to - digital converter input channel 0 9 vrl input analog - to - digital converter low - input reference 10 vrh input analog - to - digital converter high - input reference 11 vdda power analog supply voltage (+3.3vdc) 12 gnda ground analog ground 13 int0 input interrupt_0 14 int1 input interrupt_1 15 int2 input interrupt_2 16 vddc power digital core supply voltage (+2.5vdc) 17 int3 input interrupt_3 18 int4_dma0_ ack bidirectional muxed pin, inte rrupt_4 or dma channel 0 acknowledge 19 int5_dma1_ ack bidirectional muxed pin, interrupt_5 or dma channel 1 acknowledge 20 int6_dma0_ req input muxed pin, interrupt_6 or dma channel 0 request 21 int7_dma1_ req input muxed pin, interrupt_7 or dma channel 1 request 22 vddio power digital i/o supply voltage (+3.3vdc) 23 d0 bidirectional external bus interface data bit [0] 24 d1 bidirectional external bus interface data bit [1] 25 d2 bidirectional external bus interface data bit [2] 26 d3 bidirectional ex ternal bus interface data bit [3] 27 d4 bidirectional external bus interface data bit [4] 28 d5 bidirectional external bus interface data bit [5] 29 d6 bidirectional external bus interface data bit [6] 30 d7 bidirectional external bus interface data bi t [7] 31 gnd ground digital ground 32 d8 bidirectional external bus interface data bit [8] 33 d9 bidirectional external bus interface data bit [9] 34 d10 bidirectional external bus interface data bit [10] 35 d11 bidirectional external bus interface da ta bit [11] flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 74 1 - 888 - 824 - 4184 table 3 . pqfp pin listing (continued) pin signal name type description 36 d12 bidirectional external bus interface data bit [12] 37 vddio power digital i/o supply voltage (+3.3vdc) 38 d13 bidirectional external bus interface data bit [13] 39 d14 bidirectional external bus interface data bit [14] 40 d15 bidirectional external bus interface data bit [15] 41 rdy_n input external bus interface external ready indication 42 gnd ground digital ground 43 memclk output memory clock used by ext ernal memory 44 gnd ground digital ground 45 be0_n output byte enable 0, active low 46 be1_n output byte enable 1, active low 47 oe_n output output enable, active low 48 vddc power digital core supply voltage (+2.5vdc) 49 rw_n output read or write co ntrol (active low write) 50 ba_0 output bank enable 0 51 ba_1 output bank enable 1 52 cas_n output column activate signal, active low 53 gnd ground digital ground 54 ras_n output row activate signal, active low 55 cke output clock enable to be used i n conjunction with memclk 56 holdreq_n input external bus hold request, active low 57 holdgnt_n output external bus grant request, active low 58 reset _n input reset input 59 reset_out _n output reset output 60 gnd ground digital ground 61 a0 output ex ternal bus interface address bit [0] 62 a1 output external bus interface address bit [1] 63 a2 output external bus interface address bit [2] 64 a3 output external bus interface address bit [3] 65 vddio power digital i/o supply voltage (+3.3vdc) 66 a4 output external bus interface address bit [4] 67 a5 output external bus interface address bit [5] 68 a6 output external bus interface address bit [6] 69 a7 output external bus interface address bit [7] 70 gnd ground digital ground 71 a8 output externa l bus interface address bit [8] 72 a9 output external bus interface address bit [9] 73 a10 output external bus interface address bit [10] 74 a11 output external bus interface address bit [11] flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 74 1 - 888 - 824 - 4184 table 3 . pqfp pin listing (continued) pin signal name type description 75 vddc power digital core supply voltage (+2.5vdc) 76 a12 output external bus interface address bit [12] 77 a13 output external bus interface address bit [13] 78 a14 output external bus interface address bit [14] 79 a15 output external b us interface address bit [15] 80 vddc power digital core supply voltage (+2.5vdc) 81 a16 output external bus interface address bit [16] 82 a17 output external bus interface address bit [17] 83 a18 output external bus interface address bit [18] 84 a19 output external bus interface address bit [19] 85 vddio power digital i/o supply voltage (+3.3vdc) 86 a20 output external bus interface address bit [20] 87 a21 output external bus interface address bit [21] 88 a22 output external bus interface address bit [22] 89 a23 output external bus interface address bit [23] 90 gnd ground digital ground 91 a24 output external bus interface address bit [24] 92 a 25_reset_ delay internal pull - up muxed pin, external bus interface address bit [25] or por counter byp ass 93 a26_size internal pull - up muxed pin, external bus interface address bit [26] or data bus size select (0 = 8 - bit, 1= 16=bit) 94 a27_cs7_n output muxed pin, external bus interface address bit [27] or chip select 7 (chip select active low) 95 a28_c s6_n output muxed pin, external bus interface address bit [28] or chip select 6 (chip select active low) 96 a29_cs5_n output muxed pin, external bus interface address bit [29] or chip select 5 (chip select active low) 97 a30_cs4_n output muxed pin, exter nal bus interface address bit [30] or chip select 4 (chip select active low) 98 cs0_n output chip select 0 (chip select active low) 99 cs1_n output chip select 1 (chip select active low) 100 cs2_n output chip select 2 (chip select active low) 101 cs3_n output chip select 3 (chip select active low) 102 tdi input jtag data input 103 tdo output jtag data output 104 tck input jtag clock input 105 tms input jtag control signal 106 vddc power digital core supply voltage (+2.5vdc) 107 uic0_0 bidirectiona l universal i/o controller 0, pin 0 108 uic0_1 bidirectional universal i/o controller 0, pin 1 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 74 1 - 888 - 824 - 4184 table 3 . pqfp pin listing (continued) pin signal name type description 109 uic0_2 bidirectional universal i/o controller 0, pin 2 110 uic0_3 bidirectional universal i/o controller 0, pin 3 111 gnd ground digital ground 112 uic0_4 bidirectional universal i/o controller 0, pin 4 113 uic0_5 bidirectional universal i/o controller 0, pin 5 114 uic0_6 bidirectional universal i/o controller 0, pin 6 115 uic0_7 bidirectional universal i/o controller 0, pin 7 116 uic0_8 bidirectional universal i/o controller 0, pin 8 117 vddclk power supply power supply for the crystal oscillator (+2.5vdc) 118 xtal0 clock crystal input pin 0 (osc. in) 119 xtal1 clock crystal input/output pin 1 (osc. out) 120 gndclk ground digital ground 121 uic0_9 bidirectional universal i/o controller 0, pin 9 122 uic0_10 bidirectional universal i/o controller 0, pin 10 123 uic0_11 bidirectional universal i/o controller 0, pin 11 124 uic 0_12 bidirectional universal i/o controller 0, pin 12 125 uic0_13 bidirectional universal i/o controller 0, pin 13 126 uic0_14 bidirectional universal i/o controller 0, pin 14 127 uic0_15 bidirectional universal i/o controller 0, pin 15 128 uic0_16 bid irectional universal i/o controller 0, pin 16 129 uic0_17 bidirectional universal i/o controller 0, pin 17 130 gnd ground digital ground 131 uic1_0 bidirectional universal i/o controller 1, pin 0 132 uic1_1 bidirectional universal i/o controller 1, pin 1 133 uic1_2 bidirectional universal i/o controller 1, pin 2 134 uic1_3 bidirectional universal i/o controller 1, pin 3 135 vddio power digital i/o supply voltage (+3.3vdc) 136 uic1_4 bidirectional universal i/o controller 1, pin 4 137 uic1_5 bidirec tional universal i/o controller 1, pin 5 138 uic1_6 bidirectional universal i/o controller 1, pin 6 139 uic1_7 bidirectional universal i/o controller 1, pin 7 140 uic1_8 bidirectional universal i/o controller 1, pin 8 141 uic1_9 bidirectional universal i/o controller 1, pin 9 142 vddc power digital core supply voltage (+2.5vdc) 143 uic1_10 bidirectional universal i/o controller 1, pin 10 144 uic1_11 bidirectional universal i/o controller 1, pin 11 145 uic1_12 bidirectional universal i/o controller 1 , pin 12 146 uic1_13 bidirectional universal i/o controller 1, pin 13 147 uic1_14 bidirectional universal i/o controller 1, pin 14 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 74 1 - 888 - 824 - 4184 table 3 . pqfp pin listing (continued) pin signal name type description 148 gnd ground digital ground 149 uic1_15 bidir ectional universal i/o controller 1, pin 15 150 uic1_16 bidirectional universal i/o controller 1, pin 16 151 uic1_17 bidirectional universal i/o controller 1, pin 17 152 vddio power digital i/o supply voltage (+3.3vdc) 153 uic2_0 bidirectional universa l i/o controller 2, pin 0 154 uic2_1 bidirectional universal i/o controller 2, pin 1 155 uic2_2 bidirectional universal i/o controller 2, pin 2 156 uic2_3 bidirectional universal i/o controller 2, pin 3 157 vddc power digital core supply voltage (+2.5v dc) 158 uic2_4 bidirectional universal i/o controller 2, pin 4 159 uic2_5 bidirectional universal i/o controller 2, pin 5 160 uic2_6 bidirectional universal i/o controller 2, pin 6 161 uic2_7 bidirectional universal i/o controller 2, pin 7 162 gnd gro und digital ground 163 uic2_8 bidirectional universal i/o controller 2, pin 8 164 uic2_9 bidirectional universal i/o controller 2, pin 9 165 uic2_10 bidirectional universal i/o controller 2, pin 10 166 uic2_11 bidirectional universal i/o controller 2, pin 11 167 vddio power digital i/o supply voltage (+3.3vdc) 168 uic2_12 bidirectional universal i/o controller 2, pin 12 169 uic2_13 bidirectional universal i/o controller 2, pin 13 170 uic2_14 bidirectional universal i/o controller 2, pin 14 171 uic2 _15 bidirectional universal i/o controller 2, pin 15 172 gnd ground digital ground 173 uic2_16 bidirectional universal i/o controller 2, pin 16 174 uic2_17 bidirectional universal i/o controller 2, pin 17 175 uic3_0 bidirectional universal i/o controll er 3 pin 0 176 uic3_1 bidirectional universal i/o controller 3 pin 1 177 vddc power digital core supply voltage (+2.5vdc) 178 uic3_2 bidirectional universal i/o controller 3 pin 2 179 uic3_3 bidirectional universal i/o controller 3 pin 3 180 uic3_4 bi directional universal i/o controller 3 pin 4 181 uic3_5 bidirectional universal i/o controller 3 pin 5 182 gnd ground digital ground 183 uic3_6 bidirectional universal i/o controller 3 pin 6 184 uic3_7 bidirectional universal i/o controller 3 pin 7 18 5 uic3_8 bidirectional universal i/o controller 3 pin 8 186 uic3_9 bidirectional universal i/o controller 3 pin 9 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 74 1 - 888 - 824 - 4184 table 3 . pqfp pin listing (continued) pin signal name type description 187 vddio power digital i/o supply voltage (+3.3vdc) 188 uic3_10 bidirectional universal i/o controller 3 pin 10 189 uic3_11 bidirectional universal i/o controller 3 pin 11 190 uic3_12 bidirectional universal i/o controller 3 pin 12 191 uic3_13 bidirectional universal i/o controller 3 pin 13 192 gnd ground digital g round 193 uic3_14 bidirectional universal i/o controller 3 pin 14 194 uic3_15 bidirectional universal i/o controller 3 pin 15 195 uic3_16 bidirectional universal i/o controller 3 pin 16 196 uic3_17 bidirectional universal i/o controller 3 pin 17 197 t 0ic0_t0oc0 bidirectional muxed pin, timer counter unit 0 input capture 0 or output compare 0 198 t0ic1_t0oc1 bidirectional muxed pin, timer counter unit 0 input capture 1 or output compare 1 199 t0ic2_t0oc2 bidirectional muxed pin, timer counter unit 0 i nput capture 2 or output compare 2 200 t0ic3_t0oc3 bidirectional muxed pin, timer counter unit 0 input capture 3 or output compare 3 201 gnd ground digital ground 202 t1ic0_t1oc0 bidirectional muxed pin, timer counter unit 1 input capture 0 or output co mpare 0 203 t1ic1_t1oc1 bidirectional muxed pin, timer counter unit 1 input capture 1 or output compare 1 204 t1ic2_t1oc2 bidirectional muxed pin, timer counter unit 1 input capture 2 or output compare 2 205 t1ic3_t1oc3 bidirectional muxed pin, timer co unter unit 1 input capture 3 or output compare 3 206 vddc power digital core supply voltage (+2.5vdc) 207 t0in input timer counter unit 0 external clock source 208 t1in input timer counter unit 1 external clock source flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 74 1 - 888 - 824 - 4184 4.1.2 pqfp physical dimensions the phy sical dimensions for the 208 - pin pqfp package are as shown in figure 3 . legend: symbol dimension in mm dimension in inches min nom max min nom max a C C 4.07 C C 0.160 a 1 0.25 C C 0.010 C C a2 3.15 3.23 3.30 0.124 0.127 0.130 b 0.18 C 0.28 0.007 C 0.011 c 0.13 C 0.23 0.005 C 0.009 d 27.90 28.00 28.10 1.098 1.102 1.106 e 27.90 28.00 28.10 1.098 1.102 1.106 e 0.5 0 bsc 0. 02 0 bsc h d 30.35 30.60 30.85 1.195 1.205 1.215 h e 30.35 30.60 30.85 1.195 1.205 1.215 l 0.35 0.50 0.65 0.014 0.020 0.026 l 1 1.30 ref 0.051 ref y C C 0.19 C C 0.004 0 C 7 0 C 7 notes: 1. dimension d & e do not include interlead flash. 2. dimension b does not include damper protrusion/intrusion. 3. controlling dimension : mm 4. general appearance spec. should be based on visual i nspection spec. figure 3 . pqfp physical package dimensions flexible input deterministic output (fido ? ) data sheet 3 2 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 74 1 - 888 - 824 - 4184 4.2 bga 15 - by 15 - mm package 4.2.1 bga 15 - by 15 - mm pinout the pinout for the FIDO1100 communication controller bga 15 - by 15 - mm package is as shown in figure 4 . the correspondi ng pinout is provided in table 4 . f lexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller a pril 10 , 201 3 ia211080807 - 1 0 http://www.innovasic.com uncontrolled when pr inted or copied customer support : page 26 of 74 1 - 888 - 824 - 4184 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a t1ic1_ t1oc1 t0ic2_ t0oc2 t0ic0_ t0oc0 uic3_15 uic3_13 uic3_12 uic3_9 uic3_7 uic3_4 uic3_1 uic3_0 uic2_15 uic2_13 uic2_10 uic2_7 uic2_6 uic1_17 a b an_2 t1ic2_ t1oc2 t1ic0 _ t1oc0 t0ic1_ t0oc1 uic3_16 gnd uic3_11 uic3_8 uic3_5 uic3_2 uic2_17 uic2_14 uic2_11 uic2_8 uic2_5 uic2_0 uic1_14 b c an_0 an_5 t0in t1ic3_ t1oc3 t0ic3_ t0oc3 uic3_17 uic3_14 uic3_10 uic3_6 uic3_3 uic2_16 uic2_12 uic2_9 uic2_4 uic2_1 uic1_16 uic1_12 c d vdda an_1 an_6 gnd gnd t1in vddc vddc vddc vddio vddio vddio gnd gnd uic2_2 uic1_13 uic1_9 d e gnda vrh an_3 gnd gnd uic1_15 uic1_10 uic1_6 e f int2 int0 vrl an_7 uic2_3 uic1_11 uic1_8 uic1_5 f g int4_ dma0_ ack int3 int1 an_4 vddio uic1_7 uic1_4 uic1_2 g h int7_ dma1_ req int6_ dma0_ req int5_ dma1_ ack vddc vddio uic1_3 uic1_1 uic1_0 h j d0 d1 d2 vddio vddio uic0_17 uic0_16 uic0_15 j k d3 d4 d6 vddio vddc uic0_14 uic0_13 uic0_12 k l d5 d7 d11 o e_n vddc uic0_10 uic0_9 uic0_11 l m d8 d10 d15 cas_n gndclk vddclk uic0_8 xtal1 m n d9 d13 be1_n gnd gnd uic0_5 uic0_7 xtal0 n p d12 rdy_n ba_1 gnd gnd gnd reset _n vddio vddc vddc a21 a26_size gnd gnd uic0_0 uic0_4 uic0_6 p r d14 be0_n ba_0 ras_n holdgnt_n a3 a6 a10 a15 a18 a22 a27_cs7_n a29_cs5_n cs3_n cs2_n uic0_2 uic0_3 r t gnd rw_n cke reset_ out _n a2 a5 a8 a11 a14 a17 a20 a24 a28_cs6_n cs0_n cs1_n tck uic0_1 t u memclk holdreq_n a0 a1 a4 a7 a9 a12 a13 a16 a19 a23 a25_re set_ delay a30_cs4_n tdi tdo tms u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 = signals. = indicates power. = indicates ground. figure 4 . bga 15 - by 15 - mm package diagram flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 27 of 74 1 - 888 - 824 - 4184 table 4 . bga 15 - by 15 - mm package pin listing pin signal name type description f4 an_7 input analog - to - digital converter input channel 7 d3 an_6 input analog - to - digital converter input channel 6 c2 an_5 input analog - to - digital converter input channel 5 g4 an_4 input analog - to - digital converter input channel 4 e3 an_3 input analog - to - digital converter input channel 3 b1 an_2 input analog - to - digital converter input channel 2 d2 an_1 input anal og - to - digital converter input channel 1 c1 an_0 input analog - to - digital converter input channel 0 f3 vrl input analog - to - digital converter low - input reference e2 vrh input analog - to - digital converter high - input reference d1 vdda power analog supply vol tage (+3.3vdc) e1 gnda ground analog ground f2 int0 input interrupt_0 g 3 int1 input interrupt_1 f1 int2 input interrupt_2 d7 vddc power digital core supply voltage (+2.5vdc) g2 int3 input interrupt_3 g1 int4_dma0_ ack bidirectional muxed pin, interru pt_4 or dma channel 0 acknowledge h 3 int5_dma1_ ack bidirectional muxed pin, interrupt_5 or dma channel 1 acknowledge h2 int6_dma0_ req input muxed pin, interrupt_6 or dma channel 0 request h1 int7_dma1_ req input muxed pin, interrupt_7 or dma channel 1 re quest d10 vddio power digital i/o supply voltage (+3.3vdc) j1 d0 bidirectional external bus interface data bit [0] j2 d1 bidirectional external bus interface data bit [1] j3 d2 bidirectional external bus interface data bit [2] k1 d3 bidirectional exte rnal bus interface data bit [3] k2 d4 bidirectional external bus interface data bit [4] l1 d5 bidirectional external bus interface data bit [5] k3 d6 bidirectional external bus interface data bit [6] l2 d7 bidirectional external bus interface data bit [7] d4 gnd ground digital ground m1 d8 bidirectional external bus interface data bit [8] n1 d9 bidirectional external bus interface data bit [9] m2 d10 bidirectional external bus interface data bit [10] l3 d11 bidirectional external bus interface data bit [11] flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 28 of 74 1 - 888 - 824 - 4184 table 4 . bga 15 - by 15 - mm package pin listing (continued) pin signal name type description p1 d12 bidirectional external bus interface data bit [12] d11 vddio power digital i/o supply voltage (+3.3vdc) n2 d13 bidirectional external bus inte rface data bit [13] r1 d14 bidirectional external bus interface data bit [14] m3 d15 bidirectional external bus interface data bit [15] p2 rdy_n input external bus interface external ready indication t1 gnd ground digital ground u1 memclk output memor y clock used by external memory d5 gnd ground digital ground r2 be0_n output byte enable 0, active low n3 be1_n output byte enable 1, active low l4 oe_n output output enable, active low d8 vddc power digital core supply voltage (+2.5vdc) t2 rw_n outp ut read or write control (active low write) r3 ba_0 output bank enable 0 p3 ba_1 output bank enable 1 m4 cas_n output column activate signal, active low p6 gnd ground digital ground r4 ras_n output row activate signal, active low t3 cke output clock enable to be used in conjunction with memclk u2 holdreq_n input external bus hold request, active low r5 holdgnt_n output external bus grant request, active low p7 reset _n input reset input t4 reset_out _n output reset output d13 gnd ground digital gro und u3 a0 output external bus interface address bit [0] u4 a1 output external bus interface address bit [1] t5 a2 output external bus interface address bit [2] r6 a3 output external bus interface address bit [3] d12 vddio power digital i/o supply volt age (+3.3vdc) u5 a4 output external bus interface address bit [4] t6 a5 output external bus interface address bit [5] r7 a6 output external bus interface address bit [6] u6 a7 output external bus interface address bit [7] d14 gnd ground digital ground t7 a8 output external bus interface address bit [8] u7 a9 output external bus interface address bit [9] r8 a10 output external bus interface address bit [10] flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 29 of 74 1 - 888 - 824 - 4184 table 4 . bga 15 - by 15 - mm package pin listing (continued) pin signal name type description t8 a11 output external bus interface address bit [11] d9 vddc power digital core supply voltage (+2.5vdc) u8 a12 output external bus interface address bit [12] u9 a13 output external bus interface address bit [13] t9 a14 output external bus interface address bit [14] r9 a15 output external bus interface address bit [15] h4 vddc power digital core supply voltage (+2.5vdc) u10 a16 output external bus interface address bit [16] t10 a17 output external bus interface address bit [17] r10 a18 output ext ernal bus interface address bit [18] u11 a19 output external bus interface address bit [19] g14 vddio power digital i/o supply voltage (+3.3vdc) t11 a20 output external bus interface address bit [20] p11 a21 output external bus interface address bit [2 1] r11 a22 output external bus interface address bit [22] u12 a23 output external bus interface address bit [23] e4 gnd ground digital ground t12 a24 output external bus interface address bit [24] u13 a_25_reset_ delay internal pull - up muxed pin, exte rnal bus interface address bit [25] or por counter bypass p12 a_26_size internal pull - up muxed pin, external bus interface address bit [26] or data bus size select (0 = 8 - bit, 1= 16=bit) r12 a27_cs7_n output muxed pin, external bus interface address bit [27] or chip select 7 (chip select active low) t13 a28_cs6_n output muxed pin, external bus interface address bit [28] or chip select 6 (chip select active low) r13 a29_cs5_n output muxed pin, external bus interface address bit [29] or chip select 5 (ch ip select active low) u14 a30_cs4_n output muxed pin, external bus interface address bit [30] or chip select 4 (chip select active low) t14 cs0_n output chip select 0 (chip select active low) t15 cs1_n output chip select 1 (chip select active low) r15 cs2_n output chip select 2 (chip select active low) r14 cs3_n output chip select 3 (chip select active low) u15 tdi input jtag data input u16 tdo output jtag data output t16 tck input jtag clock input u17 tms input jtag control signal k14 vddc power digital core supply voltage (+2.5vdc) flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 30 of 74 1 - 888 - 824 - 4184 table 4 . bga 15 - by 15 - mm package pin listing (continued) pin signal name type description p15 uic0_0 bidirectional universal i/o controller 0, pin 0 t17 uic0_1 bidirectional universal i/o controller 0, pin 1 r16 uic0_2 bidirectional universal i/o controller 0, pin 2 r17 uic0_3 bidirectional universal i/o controller 0, pin 3 e14 gnd ground digital ground p16 uic0_4 bidirectional universal i/o controller 0, pin 4 n15 uic0_5 bidirectional universal i/o controlle r 0, pin 5 p17 uic0_6 bidirectional universal i/o controller 0, pin 6 n16 uic0_7 bidirectional universal i/o controller 0, pin 7 m16 uic0_8 bidirectional universal i/o controller 0, pin 8 m15 vddclk power supply power supply for the crystal oscillator (+2.5vdc) n17 xtal0 clock crystal input pin 0 (osc. in) m17 xtal1 clock crystal input/output pin 1 (osc. out) m14 gndclk ground digital ground l16 uic0_9 bidirectional universal i/o controller 0, pin 9 l15 uic0_10 bidirectional universal i/o controlle r 0, pin 10 l17 uic0_11 bidirectional universal i/o controller 0, pin 11 k17 uic0_12 bidirectional universal i/o controller 0, pin 12 k16 uic0_13 bidirectional universal i/o controller 0, pin 13 k15 uic0_14 bidirectional universal i/o controller 0, pin 14 j17 uic0_15 bidirectional universal i/o controller 0, pin 15 j16 uic0_16 bidirectional universal i/o controller 0, pin 16 j15 uic0_17 bidirectional universal i/o controller 0, pin 17 n4 gnd ground digital ground h17 uic1_0 bidirectional universal i/o controller 1, pin 0 h16 uic1_1 bidirectional universal i/o controller 1, pin 1 g17 uic1_2 bidirectional universal i/o controller 1, pin 2 h15 uic1_3 bidirectional universal i/o controller 1, pin 3 j4 vddio power digital i/o supply voltage (+3.3vdc) g16 uic1_4 bidirectional universal i/o controller 1, pin 4 f17 uic1_5 bidirectional universal i/o controller 1, pin 5 e17 uic1_6 bidirectional universal i/o controller 1, pin 6 g15 uic1_7 bidirectional universal i/o controller 1, pin 7 f16 uic1_8 bid irectional universal i/o controller 1, pin 8 d17 uic1_9 bidirectional universal i/o controller 1, pin 9 l14 vddc power digital core supply voltage (+2.5vdc) e16 uic1_10 bidirectional universal i/o controller 1, pin 10 f15 uic1_11 bidirectional universa l i/o controller 1, pin 11 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 31 of 74 1 - 888 - 824 - 4184 table 4 . bga 15 - by 15 - mm package pin listing (continued) pin signal name type description c17 uic1_12 bidirectional universal i/o controller 1, pin 12 d16 uic1_13 bidirectional universal i/o controller 1, pin 13 b17 uic1_1 4 bidirectional universal i/o controller 1, pin 14 n14 gnd ground digital ground e15 uic1_15 bidirectional universal i/o controller 1, pin 15 c16 uic1_16 bidirectional universal i/o controller 1, pin 16 a17 uic1_17 bidirectional universal i/o controlle r 1, pin 17 j14 vddio power digital i/o supply voltage (+3.3vdc) b16 uic2_0 bidirectional universal i/o controller 2, pin 0 c15 uic2_1 bidirectional universal i/o controller 2, pin 1 d15 uic2_2 bidirectional universal i/o controller 2, pin 2 f14 uic2_ 3 bidirectional universal i/o controller 2, pin 3 p9 vddc power digital core supply voltage (+2.5vdc) c14 uic2_4 bidirectional universal i/o controller 2, pin 4 b15 uic2_5 bidirectional universal i/o controller 2, pin 5 a16 uic2_6 bidirectional univers al i/o controller 2, pin 6 a15 uic2_7 bidirectional universal i/o controller 2, pin 7 p4 gnd ground digital ground b14 uic2_8 bidirectional universal i/o controller 2, pin 8 c13 uic2_9 bidirectional universal i/o controller 2, pin 9 a14 uic2_10 bidire ctional universal i/o controller 2, pin 10 b13 uic2_11 bidirectional universal i/o controller 2, pin 11 k4 vddio power digital i/o supply voltage (+3.3vdc) c12 uic2_12 bidirectional universal i/o controller 2, pin 12 a13 uic2_13 bidirectional universal i/o controller 2, pin 13 b12 uic2_14 bidirectional universal i/o controller 2, pin 14 a12 uic2_15 bidirectional universal i/o controller 2, pin 15 p5 gnd ground digital ground c11 uic2_16 bidirectional universal i/o controller 2, pin 16 b11 uic2_17 b idirectional universal i/o controller 2, pin 17 a11 uic3_0 bidirectional universal i/o controller 3 pin 0 a10 uic3_1 bidirectional universal i/o controller 3 pin 1 p10 vddc power digital core supply voltage (+2.5vdc) b10 uic3_2 bidirectional universal i/o controller 3 pin 2 c10 uic3_3 bidirectional universal i/o controller 3 pin 3 a9 uic3_4 bidirectional universal i/o controller 3 pin 4 b9 uic3_5 bidirectional universal i/o controller 3 pin 5 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 32 of 74 1 - 888 - 824 - 4184 table 4 . bga 15 - by 15 - mm package pin listing (continue d) pin signal name type description c9 uic3_6 bidirectional universal i/o controller 3 pin 6 a8 uic3_7 bidirectional universal i/o controller 3 pin 7 b8 uic3_8 bidirectional universal i/o controller 3 pin 8 a7 uic3_9 bidirectional universal i/o control ler 3 pin 9 p8 vddio power digital i/o supply voltage (+3.3vdc) c8 uic3_10 bidirectional universal i/o controller 3 pin 10 b7 uic3_11 bidirectional universal i/o controller 3 pin 11 a6 uic3_12 bidirectional universal i/o controller 3 pin 12 a5 uic3_13 bidirectional universal i/o controller 3 pin 13 b6 gnd ground digital ground c7 uic3_14 bidirectional universal i/o controller 3 pin 14 a4 uic3_15 bidirectional universal i/o controller 3 pin 15 b5 uic3_16 bidirectional universal i/o controller 3 pin 16 c6 uic3_17 bidirectional universal i/o controller 3 pin 17 a3 t0ic0_t0oc0 bidirectional muxed pin, timer counter unit 0 input capture 0 or output compare 0 b4 t0ic1_t0oc1 bidirectional muxed pin, timer counter unit 0 input capture 1 or output compare 1 a2 t0ic2_t0oc2 bidirectional muxed pin, timer counter unit 0 input capture 2 or output compare 2 c5 t0ic3_t0oc3 bidirectional muxed pin, timer counter unit 0 input capture 3 or output compare 3 p13 gnd ground digital ground b3 t1ic0_t1oc0 bidirectio nal muxed pin, timer counter unit 1 input capture 0 or output compare 0 a1 t1ic1_t1oc1 bidirectional muxed pin, timer counter unit 1 input capture 1 or output compare 1 b2 t1ic2_t1oc2 bidirectional muxed pin, timer counter unit 1 input capture 2 or outpu t compare 2 c4 t1ic3_t1oc3 bidirectional muxed pin, timer counter unit 1 input capture 3 or output compare 3 c3 t0in input timer counter unit 0 external clock source d6 t1in input timer counter unit 1 external clock source p14 gnd ground digital ground h14 vddio power digital i/o supply voltage (+3.3vdc) flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 33 of 74 1 - 888 - 824 - 4184 4.2.2 bga 15 - by 15 - mm physical package dimensions the physical dimensions for the bga 15 - by 15 - mm package are as shown in figure 5 . legend: symbol dimension in mm dimens ion in inches min nom max min nom max a C C 1.20 C C 0.047 a1 0.16 0.21 0.26 0.006 0.008 0.010 a2 0.84 0.89 0.94 0.033 0.035 0.037 c 0.32 0.36 0.40 0.013 0.014 0.016 d 14.90 15.00 15.10 0.587 0.591 0.594 e 14.90 15.00 15.10 0.587 0.591 0.594 d1 C 12.80 C C 0.504 C e1 C 12.80 C C 0.504 C e C 0.80 C C 0.031 C b 0.25 0.30 0.35 0.010 0.012 0.014 aaa 0.10 0.004 bbb 0.10 0.004 ddd 0.12 0.005 eee 0.15 0.006 fff 0.08 0.003 md/me 17/17 17/17 figure 5 . bga 15 - by 15 - mm physical package dimensions notes: 1. controlling dimension: millimeter. 2. primary datum c and seating plane are defined by the spherical crowns of the solder ba lls. 3. dimension b is measured at the maximum solder - ball diameter, parallel to primary datum c. 4. there will be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. 5. special characteristics c class: bbb ddd. 6. the pattern of pin 1 fiducial is for reference only. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 34 of 74 1 - 888 - 824 - 4184 4.2.3 bga 15 - by 15 - mm signal routing the 15 - by15 - mm bga can be easily routed using economical and readily available pcb fabrication design rules. in order to route all signals from the FIDO1100 bga, 2 layers in addition to power and ground are required, using 0.1mm trace/space technology. since 0.1mm = 3.937mil, most pcb fabricators will consider this 4mil trace/space. the pcb land pattern for the bga should use 0.3mm round pads. since the bga pitch is 0.8mm , this leaves 0.5mm of space between pads. using 0.1mm trace/space, 2 signals may be routed between each pair of pads (2 traces + 3spaces = 0.5mm). figure 8 shows how this is accomplished. referring to figure 6 , signal layer 1 is shown in black, signal la yer 2 is shown in red, and the vias are shown in blue. signal layer 1 is the top side with the bga pads, while signal layer 2 may be any other layer, but is typically the bottom side. all vias with no trace routed out from the bga are power or ground. not e that the innermost row of pads is all power and ground, except for 9 pads which are signals. three of these signals are easily routed on signal layer 1, but 6 of them require the use of vias and signal layer 2. if all of the signals are not required for a given design, it may be possible to route all of the used signals on signal layer 1. it may be beneficial to place more vias and to route more signals on layers other than signal layer 1. this could produce a better pcb layout, but care should be exerc ised to not include an excessive number of vias. the use of too many vias can lead to inadequate copper on the power/ground plane layers surrounding the center area of the bga, resulting in relative isolation of the bga power/ground via connections. note the open space between pads m17 and n17 (a1 is upper left corner). these signals are xtal1 and xtal0. it is best not to route other signals between these pads, especially if a crystal is used for the clock source. the power connections to the inner ring o f pads have 4 vias for +3.3v and 4 vias for +2.5v. the use of a single bypass capacitor for each via, and alternating 0.1uf and 0.01uf values on each supply, provide reasonable bypass capacitance for the FIDO1100. using 8 capacitors in this manner allows t he use of capacitors in the 0603 package for economical pcb assembly. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 35 of 74 1 - 888 - 824 - 4184 figure 6 . bga 15 - by 15 - mm signal routing flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 36 of 74 1 - 888 - 824 - 4184 4.3 power and ground signals tables 5 - 9 provide analog power and ground signals , crystal oscillator power and gr ound signals , 2.5 vdc digital core power signals , 3.3 vdc digital io power signals , and digital ground signals , respectively. the recommended bypass capacitors for the FIDO1100 are: use a mix of 0.1 f and 0.01 f capacitors. bypass capacitors should be located as close as possible to power pins they are connected to. table 5 . analog power and ground signals pqfp bga 15 x 15 signal name type description 11 d1 vdda power analog supply voltage (+3.3vdc) 12 e1 gnda ground analog ground table 6 . crystal oscillator power and ground signals pqfp bga 15 x 15 signal name type description 117 m15 vddclk power supply power supply for the crystal oscillator (+2.5vdc) 120 m14 gndclk ground digital ground ta ble 7 . 2.5 vdc digital core power signals pqfp bga 15 x 15 signal name type description 16 d7 vddc power digital core supply voltage (+2.5vdc) 48 d8 vddc power digital core supply voltage (+2.5vdc) 75 d9 vddc power digital cor e supply voltage (+2.5vdc) 80 h4 vddc power digital core supply voltage (+2.5vdc) 106 k14 vddc power digital core supply voltage (+2.5vdc) 142 l14 vddc power digital core supply voltage (+2.5vdc) 157 p9 vddc power digital core supply voltage (+2.5vdc) 177 p10 vddc power digital core supply voltage (+2.5vdc) 206 C vddc power digital core supply voltage (+2.5vdc) C C vddc power digital core supply voltage (+2.5vdc) flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 37 of 74 1 - 888 - 824 - 4184 table 8 . 3.3 vdc digital io power signals pqfp bga 15 x 15 signal name type description 22 d10 vddio power digital i/o supply voltage (+3.3vdc) 37 d11 vddio power digital i/o supply voltage (+3.3vdc) 65 d12 vddio power digital i/o supply voltage (+3.3vdc) 85 g14 vddio power digital i/o supply voltage (+3.3vdc) 135 j4 vddio power digital i/o supply voltage (+3.3vdc) 152 j14 vddio power digital i/o supply voltage (+3.3vdc) 167 k4 vddio power digital i/o supply voltage (+3.3vdc) 187 p8 vddio power digital i/o supply voltage (+3.3vdc) C h14 vddio power digital i/o supply voltage (+3.3vdc) table 9 . digital ground signals pqfp bga 15 x 15 signal name type description 31 d4 gnd ground digital ground 42 t1 gnd ground digital ground 44 d5 gnd ground digital ground 53 p6 gnd ground di gital ground 60 d13 gnd ground digital ground 70 d14 gnd ground digital ground 90 e4 gnd ground digital ground 111 e14 gnd ground digital ground 130 n4 gnd ground digital ground 148 n14 gnd ground digital ground 162 p4 gnd ground digital ground 172 p5 gnd ground digital ground 182 b6 gnd ground digital ground 192 p13 gnd ground digital ground 201 p14 gnd ground digital ground C C gnd ground digital ground flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 38 of 74 1 - 888 - 824 - 4184 5. electrical characteristics tables 10 - 14 show the absolute maximum ratings, esd and latc h - up characteristics, recommended operating conditions, dc characteristics, and input impedance, respectively. table 10 . absolute maximum ratings symbol parameter name conditions min typ max units v ddc digital core supply voltage C - 0.3 C 3.05 v v ddio digital i/o supply voltage C - 0.3 C 5.5 v v ain analog input voltage with respect to ground C - 0.3 C 3.9 v t a ambient temperature C - 40 C +85 o c t s storage temperature C - 55 C +150 o c t j junction temperature C - 40 C +125 o c note : operation of the FIDO1100 outside of maximum operating ratings may result in failure of the device. table 11 . esd and latch - up characteristics symbol parameter name conditions min typ max units v hbm human body model C 2000 C C v v mm machine model C 200 C C v i latp positive latch - up current C C C 50 a i latn negative latch - up current C C C - 50 a table 12 . recommended operating conditions symbol parameter name conditions min typ max units v ddc dig ital core supply voltage C 2.25 2.5 2.75 v v ddio digital i/o supply voltage C 3.0 3.3 3.6 v f xtal crystal frequency C C C 66 mhz t a ambient temperature C - 40 C +85 o c v dda analog supply voltage C 3.0 3.3 3.6 v v rh adc reference voltage high C C 3.0 C v v rl adc reference voltage low C C 0 C v c l digital output load capacitance see note C 3.1 C pf note: this parameter is guaranteed by design and not tested in production. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 39 of 74 1 - 888 - 824 - 4184 table 13 . dc characteristics t a = C 40 o c and +85 o c; v ddc = 2.5v 10%; v ddio = 3.3v 10%; f clk = 66mhz symbol parameter name conditions min typ max units v ih input high voltage C C C il input low voltage C C C lkg input leakage current C in input capacitance C C C oh output high voltage |ioh| = 8 ma 2.4 C C ol output low voltage |iol| = 8 ma C C oz tri - state leakage C out package output capacitance C C C table 14 . input impedance input leakag e current: 10 a with no pull - up/pull - down tristate leakage current: 10 a pin capacitance (input or output): ~3.5 pf not including package contribution table 15 . ac characteristics of crystal oscillator symbol paramet er conditions typ max units f osc crystal oscillator range ta = 25oc C 66 mhz t st startup time ta = 25oc 20 C m s flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 40 of 74 1 - 888 - 824 - 4184 table 16 . analog - to - digital converter characteristics symbol parameter name conditions min typ max units v ina inp ut voltage range C 0.1v dda - 0.9v dda v c ina input capacitance C C 20 C pf res resolution C C 10 C bits inl integral non - linearity C C 2 C lsb dnl differential non - linearity guaranteed no missing codes C 1 C lsb sinad signal to noise plus distortio n fin = 10 khz C 54 C db fsmpl sample clock frequency C 0.5 C 2.6 mhz p d power dissipation ta = 25oc C 5 C mw smp sample rate C C C 200 ksps notes: 1. the adc in the FIDO1100 uses its own vdd (vdda) and gnd (gnda) connections along with vref high (vrh) a nd vref low (vrl) signals. 2. vrh must be less than or equal to vdda. 3. vrl must be greater than or equal to gnda. 4. to ensure maximum conversion accuracy, vdda, gnda, vrh, and vrl should be as clean and free of noise as possible. table 17 . power consumption conditions core voltage 2.5 vdc i/o voltage 3.3 vdc total current power current power power halted after a reset 109.240 ma 273.100 mw 2.500 ma 8.25 mw 281.35 mw light processing load 214.000 ma 535.000 mw 7.700 ma 25.41 mw 560.4 1 mw heavy processing load 227.000 ma 567.500 mw 17.000 ma 56.1 mw 623.60 mw sleep mode 320.90 mw stop mode 302.91 mw low power stop mode (lpstop) 8.68 mw flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 41 of 74 1 - 888 - 824 - 4184 6. thermal characteristics the thermal resistance characteristics for the 28 x 2 8 mm pqfp and the 15 x 15 mm bga packages are provided in table 18 . all data is simulated based on the 2s2p board type. the board type is defined by jedec standard jesd51 - 7 for the pqfp package and by jesd51 - 9 for the bga package. table 18 . thermal resistance characteristics name description airflow (m/s) 15 x 15 mm bga 28 x 28 mm pqfp jc ( c/w) junction to case 0 7.2 16.3 ja ( c/w) junction to ambient 0 56.8 35.1 ja ( c/w) junction to ambient 1 51.1 30.9 ja ( c/w) junction to ambient 2 48.8 28.7 ja ( c/w) junction to ambient 3 47.2 27.5 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 42 of 74 1 - 888 - 824 - 4184 7. reset 7.1 overview this se ction describes the reset signal considerations and the reset timing. the power on reset register has a control bit to determine whether major reset or minor reset processing is performed after reset is asserted. the section below presents the hardware s ignal characteristics. see the FIDO1100 user guide for more details on the power on reset control register. 7.2 signal considerations and reset timing the FIDO1100 requires the reset_n signal to be asserted low for a minimum of 100 s after vddio and vddc are at their nominal values and stable. the reset_n signal must have a rise time of less than 100 ns. table 19 presents the hardware signals involved or affected and should be considered when asserting reset. table 19 . hardware sign als involved when asserting reset signal name type description reset _n input reset input reset_out _n output reset output a_25_reset_delay muxed, internal pull - up muxed pin, external bus interface address bit [25] or por counter bypass a_26_size muxed, internal pull - up muxed pin, external bus interface address bit [26] or data bus size select (0 = 8 - bit, 1 = 16 - bit) a27_cs7_n muxed muxed pin, external bus interface address bit [27] or chip select 7 (chip select active low) a28_cs6_n muxed muxed pin, e xternal bus interface address bit [28] or chip select 6 (chip select active low) a29_cs5_n muxed muxed pin, external bus interface address bit [29] or chip select 5 (chip select active low) a30_cs4_n muxed muxed pin, external bus interface address bit [3 0] or chip select 4 (chip select active low) cs0_n output chip select 0 (chip select active low) when reset _n is asserted, the following sequence occurs: the a25_reset_delay signal is sampled to determine the length of the reset clock delay C low reset cl ock delay 100 secs C high reset clock delay 20 msecs note: after this delay, the part performs major or minor reset processing and is released to run. the a_26_size pin is sampled for the external bus interface size C low 8 - bit width C high 16 - bit width flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 43 of 74 1 - 888 - 824 - 4184 th e reset_out _n signal is driven low for the determined clock delay figures 7 and 8 present the reset timing and extended reset timing diagrams, respectively. the a_26_size signal is not shown, but it is sampled. figure 7 . reset t iming figure 8 . extended reset timing note: if a25_ reset_delay is high at the rising edge of reset _n , internal reset and reset_out_n are extended from 100 s to 20 ms. c l k r e s e t _ n r e s e t _ o u t _ n r e s e t _ d e l a y a d d r 2 4 : 0 d a t a 1 5 : 0 c s 0 timegen 0x000000 100us power on reset clock running | <--- clock stable 0x000000 100s 100us hardware reset (addr 25) clk reset reset_out reset_delay addr 24:0 data 15:0 cs0 c l k r e s e t _ n r e s e t _ o u t _ n r e s e t _ d e l a y a d d r 2 4 : 0 d a t a 1 5 : 0 c s 0 timegen 0x000000 20ms power on reset clock running | <--- clock stable 0x000000 100s 20ms hardware reset (addr 25) (addr 25) clk reset reset_out reset_delay addr 24:0 data 15:0 cs0 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 44 of 74 1 - 888 - 824 - 4184 the following multiplexed signals are tri - stated during re set and should be pulled high if being used as chip selects or pulled low if being used as address lines (the FIDO1100 boots at address 0x00000000). if not being used, they can be pulled either high or low. a27_cs7_n a28_cs6_n a29_cs5_n a30_cs4_n at rese t, the cs0_n signal defaults to low for external memory access, supporting the boot sequence from address 0x00000000. 7.3 clock signals 7.4 typical clock source implementations the FIDO1100 can operate in one of two modes: (1) normal or driven clock source input or (2) using an external crystal to set the operating frequency of the internal oscillator. note: vdd clk and gnd clk must be connected even when not using an external crystal. 7.4.1 normal or driven clock source system configuration drive external clock sou rce into xtal0 (see figure 9 ). xtal1 is left unconnected. xtal0 is effectively a schmitt trigger input. target frequency should have a duty cycle of approximately 40% to 60%. 7.4.2 using an external crystal system configuration (third overtone) crystal across xtal0/xtal1 (see figure 10 ), 36 pf load caps to ground, 0.1 - f cap, and 0.33 - h inductor in series from xtal1 to ground. system configuration (fundamental tone) crystal across xtal0/xtal1 (see figure 11 ) and 20 - pf load caps to ground. note: load capacit or and inductor values may be different based on crystal used. please consult with your crystal supplier for more information. third overtone configuration is recommended for 24 - to 66 - mhz operation and fundamental tone configuration is recommended for 1 - to 24 - mhz operation. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 45 of 74 1 - 888 - 824 - 4184 c lk vcc figure 9 . driven clock source figure 10 . crystal oscillator third overtone off - chip components figure 11 . crystal oscillator fundamental overtone off - chip components g n d c l k n o t c o n n e c t e d f i d o 1 1 0 0 x t a l 0 e x t e r n a l c l o c k s o u r c e 2 . 5 v x t a l 1 v d d c l k g n d c l k f i d o 1 1 0 0 x t a l 0 2 . 5 v x t a l 1 v d d c l k c r y s t a l l 1 c 3 c 2 c 1 g n d c l k f i d o 1 1 0 0 x t a l 0 2 . 5 v x t a l 1 v d d c l k c r y s t a l c 2 c 1 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 46 of 74 1 - 888 - 824 - 4184 7.5 off - chip component value table 20 shows the suggested off - chip component values: table 20 . suggested off - chip component values operating frequency c1 c2 c3 l1 66mhz 36pf 36pf 0.1 f 330nh 20 mhz 20pf 20p f na na notes : 1. different c1, c2 values lead to different oscillation characteristics and should be selected based on system (board) level considerations. 2. u sing c1 = c2 is recommended . flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 47 of 7 4 1 - 888 - 824 - 4184 8. signals 8.1 external bus operation 8.1.1 overview the FIDO1100 interfaces to external memory and peripherals through a set of programmable chip - select and bus - timing registers. it also has a built - in sdram controller to interface to sdram. this chapter provides timing diagrams for hardware considerations. for definitions of re gisters that control external bus timing an d the sdram timing, please see t he FIDO1100 user guide . the external a ddress bus of the FIDO1100 is 31 - bit, and the external data bus is configurable to support either an 8 - or 16 - bit bus. in this section , timing diagrams are provided for the following: general setup and hold timing external bus timing C 32 - bit transfer w ithou t external ready (rdy_n) C 32 - bit transfer with external ready (rdy_n) C 8 - bit/16 - bit single cycle without external ready (rdy_n) C 8 - bit/16 - bit cycle with external ready (rdy_n) sdram timing C sdram cas timing C sdram row activation timing C sdram read operation timing C sdram read burst timing C sdram write operation, write burst, write - to - write operation, and write - to - precharge timing 8.2 general setup and hold timing all timing delay s are characterized at the 50% to 50% point. this includes propagation delay times through combinatorial functions as well a s setup, hold time, and release - time definitions for sequential elements (see chapter 9, set up and hold timing , for diagrams). flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 48 of 74 1 - 888 - 824 - 4184 8.3 external bus timing s ignals listed on the external bus timing diagrams are described below. twwait C if rdy_enable=0, specifies the width of the chip select active period for the non - burst - mode write cycle. the allowed r ange is 0 C 31 , resulting in a wait time o f 1 C 32 clocks. C if rdy_enable=1, specifies the wait time before the rdy_n line is first sampled for the write cycle. this provides a max wait time of 484 ns at 66 mhz. anything greater than this will require the ext ernal rdy_n line and external logic. trwait C if rdy_enable=0 , specifies the width of the chip select active period for the non - burst - mode read cycle. the allowed range is 0 C 31 , resulting in a wait time of 1 C 32 clocks. C if rdy_enable=1, specifies the wait time before the rdy_n line is first sampled for the read cycle. this provides a max wait time of 484 ns at 66 mhz. anything greater than this will require the external rdy_n line and external logic. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 49 of 74 1 - 888 - 824 - 4184 9. setup and hold timing all timing delays are character ized at the 50% to 50% point. this includes propagation delay times through combinatorial f unctions as well as setup, hold - time, and release - time definitions for sequential elements. propagation delay time between an input signal transition and the result ant output signal transition (see figure 1 2 ). tplh = 14ns . tphl = 14ns . figure 12 . propagation delay setup time the minimum time that input data must remain unchanged prior to an active clock transition (see figure 1 3 ). setu p = 2ns . figure 13 . setup time flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 50 of 74 1 - 888 - 824 - 4184 hold time the minimum time that input data must remain unchanged subsequent to an active clock transition (see figure 1 4 ). hold = 2ns . figure 14 . hold time recovery tim e the minimum time that the se t or reset input must remain un activated prior to an active clock transition (see figure 1 5 ). recovery = 3ns . figure 15 . recovery time removal time the minimum time that the set or reset input must remain activated subsequent to an active clock transition (see figure 1 6 ). removal = 3ns . figure 16 . removal time flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 51 of 74 1 - 888 - 824 - 4184 minimum pulse width the minimum length of time between the leading and trailing edges of a pulse (see figure 1 7 ). timings are based on a 66 - mhz clock yielding 15 - ns cycles. mpw_h = 7ns. mpw_l = 7ns . figure 17 . minimum pulse width thld specifies the time between when the csn_n and ben_n signals go inactive (hi) and the address is removed, 0 C 7 clocks. tcs specifies the time between when the address bus is driven and the csn_n and ben_n signals go active (low), 0 C 3 clocks. toe specifies the time between when the csn_n and ben_n signals go active (low) and the oe signal goes active (low), 0 C 3 clocks. twef specifies the time between when the csn_n and ben_n signals go active (low) and the we_n signal goes active (low), 0 C 3 clocks. twer specifies the time between when the we_n signal goes inactive (hi) and the csn_n and ben_n signals go inac tive (hi), 0 C 3 clocks. 9.1.1 external bus timing for a 32 - bit transfer (without rdy_n) this timing is programmable via the external bus chip select timing register (see figure 18 ). all timing is relative to the rising edge of the clock. the chip - select and byte - enable signals (csn_n and ben_n) go active (low) 0 C 3 clocks (tcs) after the address bus is driven. the chip - select, output - enable, and byte - enable signals (csn_n, ben_n , and oe_n) go inactive (hi) 0 C 7 clocks (thld) before the address is removed (on the la st cycle). flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 52 of 74 1 - 888 - 824 - 4184 figure 18 . external bus timing for a single, 32 - bit cycle (without rdy_n) the write - cycle timing is controlled by twwait setting (shown as txw ait in the diagram), 1 C 16 clocks . the read - cycle timing is controlled by tr wait setting (shown as txwait in the diagram ), 1 C 16 clocks . the output - enable signal (oe_n) goes active (low) 0 C 3 clocks (toe) after the chip select. the output - enable signal (oe_n) goes inactive (hi) coincident with the chip select. the write - enable signa l (we_n) goes active (low) 0 C 3 clocks (twef) after the chip select (first cycle only). for subsequent cycles, the we_n line will go active (low) 0 C 3 clocks (twef) after the address bus changes. the write - enable signal (we_n) goes inactive (hi) 0 C 3 clocks (twer) before the end of the wait time and hence before the address bus changes (subsequent cycles). this is when the data is considered written. 9.1.2 external bus timing for a 32 - bit transfer (with rdy_n) this timing is programmable via the external bus chi p select timing register (see figure 19 ). flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 53 of 74 1 - 888 - 824 - 4184 figure 19 . external bus timing for a 32 - bit transfer (with rdy_n) the txwait setting determines when first to start sampling the low active rdy_n line (labeled with an arrow marked 1 in the diagram). in the case of a write transfer after the low active rdy_n line is first sampled low (labeled with an arrow marked 2 in the diagram), the write cycle will complete on the next rising edge of the clock as shown (labeled with an arrow mark ed 3 in the diagram). in the case of a read transfer once the low active rdy_n line is first sampled low (labeled with an arrow marked 2 in the diagram), the read data will be sampled on the second rising edge of the clock. the write - cycle timing is c ontrolled by twwait setting (shown as txwait in the diagram ), 1 C 16 clocks . the read - cycle timing is controlled by trwait setting (shown as txw ait in the diagram), 1 C 16 clocks . if the rdy_n line never goes low, the cycle will end (as a bus error) after a ti meout of txwait + 256 clocks. if the rdy_n line is unused (tied low via an internal pull down) or goes low immediately, the cycle will be controlled by txwait as described above. in the case of a write transfer, the write - enable signal (we_n) goes active ( low) 0 C 3 clocks after the cs_n goes low. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 54 of 74 1 - 888 - 824 - 4184 the write - enable signal (we_n) goes inactive (hi) 0 C 3 clocks (twer) before the end of the chip - select time. 9.1.3 external bus timing for 8 - bit/16 - bit transfer (without rdy_n) this timing is programmable via the external bus chip select control register (see figure 2 0 ). figure 20 . external bus timing for 8 - bit/16 - bit transfer (without rdy_n) all timing is relative to the rising edge of the clock. the chip - select and byte - enable signals (csn_n an d ben_n) go active (low) 0 C 3 clocks (tcs) after the address bus is driven. the chip - select and byte - enable signals (csn_n and ben_n) go inactive (hi) 0 C 7 clocks (thld) before the address is changed. the write - cycle timing is controlled by twwait setting (s hown as txwait in the diagram ), 1 C 16 clocks . the read - cycle timing is controlled by trwait setting (shown as txwa it in the diagram), 1 C 16 clocks . flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 55 of 74 1 - 888 - 824 - 4184 the output - enable signal (oe_n) goes active (low) 0 C 3 clocks (toe) after the chip select. the output - enable s ignal (oe_n) goes inactive (hi) coincident with the chip select. this is also when the read data is sampled. the write - enable signal (we_n) goes active (low) 0 C 3 clocks (twef) after the chip select. the write - enable signal (we_n) goes inactive (hi) 0 C 3 cl ocks (twer) before the end of the cycle (csn_n is removed). 9.1.4 external bus timing for 8 - bit/16 - bit transfer (with rdy_n) this timing is programmable via the external bus chip select control register (see figure 2 1 ). figure 21 . exte rnal bus timing for 8 - bit/16 - bit transfer (with rdy_n) the write - cycle timing is controlled by twwait setting (shown as txw ait in the diagram), 1 C 16 clocks . the read - cycle timing is controlled by trwait setting (shown as txwait in the diagram ), 1 C 16 clock s . the txwait setting determines when first to start sampling the low active rdy_n line (labeled with an arrow marked 1 in the diagram). flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 56 of 74 1 - 888 - 824 - 4184 in the case of a write transfer, once the low active rdy_n line is first sampled low (labeled with an arrow marked 2 in the diagram), the write cycle will complete on the next rising edge of the clock as shown (labeled with an arrow marked 3 in the diagram). in the case of a read transfer, once the low active rdy_n line is first sampled low (labeled with an arrow mar ked 2 in the diagram), the read data will be sampled on the second rising edge of the clock . if the rdy_n line never goes low, the cycle will end (as a bus error) after a timeout of txwait + 256 clocks. if the rdy_n line is unused (tied low via an intern al pull down) or goes low immediately, the cycle will be controlled by txwait as shown above. in the case of a write transfer, the write enable signal (we_n) goes active (low) 0 C 3 clocks after the cs_n goes low. the write enable signal (we_n) goes inactive (hi) 0 C 3 clocks (twer) before the end of the chip - select time. note: this timing picture also reflects the default bus timing for all memory addresses not decoded by the internal chip - select unit. in this case, the timing is controlled by the external b us default timing register. 9.2 sdram timing 9.2.1 sdram cas timing the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving because of the clock edge one cycle earlier ( n + m C 1) and , provided the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming the clock cycle time is such that all relevant access times are met , i f a read command is registered at t0 and the latency is programmed to two clocks, the dqs will start driving after t1 a nd the data will be valid by t2, as shown in figure 2 2 . flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 57 of 74 1 - 888 - 824 - 4184 figure 22 . sdram cas timing 9.2.2 sdram row activation timing before any read or write commands can be issued to a bank within the sdram, a row in that bank must be opened. this is accomplished via the active command, which selects both the bank and the row to be activated (see figure 2 3 ). after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the trcd specification. t he trcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a trcd s pecification of 20ns with a 125 - mhz clock (8 - ns period) results in 2.5 clocks, rounded to 3. this is reflected in figure 2 4 , which covers any case where 2 < trcd (min)/tck 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 58 of 74 1 - 888 - 824 - 4184 figure 23 . specific row activation timing figure 24 . meeting trcd (min) when 2 < trcd (min)/tck 3 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 59 of 74 1 - 888 - 824 - 4184 9.2.3 sdram read operation timing read bursts are initiated with a read command. the starting column and bank addresses are provided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the generic read commands used in the following illustrations, auto precharge is disabled (see figure 2 5 ) . figure 25 . sdram read ope ration timing during read bursts, the valid data - out element from the starting column address will be available following the cas latency after the read command. each subsequent data - out element will be valid by the next positive clock edge. upon comple tion of a burst, assuming no other commands have been initiated, the dqs will go high, and full - page burst will continue until terminated. (at end of the page, it will wrap to column 0 and continue.) 9.2.4 sdram read burst timing data from any read burst may be truncated with subsequent read command, and data from a fixed - length read burst may be immediately followed by data from a read command. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows eithe r the last element of a completed burst or the last desired data element of a flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 60 of 74 1 - 888 - 824 - 4184 longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the ca s latency minus one (see figure 2 6 ) . for cas latencies of two and three, data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the 64 mbyte sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a read command can be initiated on any clock cycle following a previous read command. full - speed random read accesses can be performed to the same bank, as shown in figure 1 6 or each subsequent read may be performed to a different bank. figure 26 . sdram read burst timing 9.2.5 sdram write operation, write burst, write - to - write, and write - to - precharge timing write bursts are initiated with a write command. the starting column and bank ad dresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 61 of 74 1 - 888 - 824 - 4184 being accessed is precharged at the completion of the burst. for the generic write commands used in the f ollowing illustrations, auto precharge is disabled. during write bursts, the first valid data - in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon comple tion of a fixed - length burst, assuming no other commands have been initiated, the dqs will remain high - z, and any additional input data will be ignored. a full - page burst will continue until terminated. (at the end of the page, it will wrap to column 0 a nd continue.) data for any write burst may be truncated with a subsequent write command, and data for a fixed length write burst may be immediately followed by data for a write command. the new write command can be issued on any clock following the previo us write command, and the data provided coincident with the new command applies to the new command (see figure s 27 - 30 ). figure 27 . sdram write operation timing flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 62 of 74 1 - 888 - 824 - 4184 figure 28 . sdram write burst timing f igure 29 . sdram write - to - write timing flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 63 of 74 1 - 888 - 824 - 4184 figure 3 0 . sdram write - to - precharge timing flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 64 of 74 1 - 888 - 824 - 4184 10. jtag the tap controller is a synchronous finite state machine and responds to changes in the tms and tck signals. stat es transition occurs on the rising edge of tck. values shown to the side of each state represent the state of tms at the time of the rising edge of tck (see figure 3 1 ) . there are two paths through the state machine. the instruction path captures and loa ds the jtag instructions into the instruction register. the data path captures and loads data into the other three registers. the tap controller executes the last instruction decode until a new instruction is entered at the update - ir state or until a res et is sent to the controller. figure 31 . jtag state machine the jtag port has four read/write registers. an id register, by - pass register, boundary scan, and instruction register (see figure 3 2 ) . the tdo pin remains in the hi gh impedance state except during a shift - dr or shift - ir controller state. in the shift - dr and shift - ir controller states, tdo is updated on the falling edge of tck. tms and tdi are sampled on the rising edge of tck. t e s t - l o g i c - r e s e t r u n - t e s t / i d l e s e l e c t - d r - s c a n c a p t u r e - d r s h i f t - d r e x i t 1 - d r p a u s e - d r e x i t 2 - d r u p d a t e - d r s e l e c t - i r - s c a n c a p t u r e - i r s h i f t - i r e x i t 1 - i r p a u s e - i r e x i t 2 - i r u p d a t e - i r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 65 of 74 1 - 888 - 824 - 4184 figure 32 . jtag port register interface the timing of the jtag signals is shown in figure 3 3 . the tdo pin remains in the high impedance state except during a shift - dr or shift - ir controller state. in the shift - dr and shift - ir controller states, tdo is updated on the falling edge of tck. tms and tdi are sampled on the rising edge of tck. figure 33 . timing of jtag signals 10.1 jtag scan chain debug functionality the jtag port contains an 8 - bit - wide instruction register. instructions are tr ansferred to this register during the shift - ir state of the tap state machine and are decoded by entering the update - ir state of the tap. the jtag controller executes the last decoded instruction until another new one is entered and decoded. the instruct ions and data are entered serially through the tdi pin, lsb first. the jtag test access port (tap) instruction shift register will support the debug scan chain commands shown in table 2 1 . i d r e g i s t e r b y - p a s s r e g i s t e r b o u n d a r y s c a n i n s t r u c t i o n r e g i s t e r i n s t r u c t i o n d e c o d e t a p c o n t r o l l e r i n p u t m u x o u t p u t m u x t m s t c k t d o t d i flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 66 of 74 1 - 888 - 824 - 4184 table 21 . debug scan chain commands suppo rted by the jtag tap jtag instruction scan chain function scan chain length scan chain reference number public or private 00010000 readwriteaddrcmd (read/write memory/registers address and command) 37 bits 1 private 00010001 readdata (read memory/registe rs data) 32 bits 2 private 00010010 writedata (write memory/registers data) 32 bits 7 private 00010011 readpc_andcontext (read program counter and active context) 37 bits 4 private 00010100 readwritedrbugreg (read/write debug control register) 15 bits 5 private 11111110 idcode (read device id register) 32 bits 3 public 11111000 extest (io boundary scan) n bits (i/o pins) 6 public 11111010 sample/preload (sample boundary scan chain on capture - dr state, load boundary scan chain on update - dr state) n bits (i/o pins) 6 public 11111111 bypass (use tdi/tdo bypass register) 1 bit 9 public 00000111 runbist (run built in self - test ) 16 bits 8 public 00001111 enableatpg (enable atpg mode for manufacturing test) n/a n/a private notes: 1. the boundary - scan sc an chain is selected via the exetest, sample, and preload instructions. 2. the sample and preload instructions have the same binary code. (they are identified as separate instructions in the jtag spec, but are allowed to have the same binary code for backwar ds compatibility with previous version of spec.) 3. any undefined bit pattern that is shifted into the instruction register will perform the same function as the bypass instruction. 4. on power - on reset, or when the jtag st ate machine enters the test logic rese t the instruction register will reset its value to operate as the idcode instruction (per jtag spec). flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 67 of 74 1 - 888 - 824 - 4184 11. ordering information the FIDO1100 parts currently available are listed in table 2 2 . table 22 . part numbers by package types innovasic part number package type temperature grade FIDO1100 pqf208ir 1 lead - free ( rohs - compliant ) 208 - lead qfp 28 - by 28 - mm package industrial FIDO1100bgb208ir 1 lead - free ( rohs - compliant ) 208 - ball bga, .8mm pitch 15 - by 15 - mm package industrial flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 68 of 74 1 - 888 - 824 - 4184 12. err ata this chapter addresses issues discovered by our internal testing organization that may affect the implementation of the FIDO1100. this information should be used in conjunction with the FIDO1100 user guide and the FIDO1100 instruction set reference gu ide to circumvent problems during the design process and is not intended as a standalone design guide. although FIDO1100 - specific terms are clearly de scribed, in the interest of conciseness, many terms already familiar to designers and developers are left undefined. 12.1 summary table 2 3 presents a summary of errata. table 23 . summary of errata errata no. problem ver. 1 1 adc start register bit 0 (start) does not self - clear when non - scanning mode conversion for single channel or mult i - channel is selected. exists 2 fatal fault recovery sequence can be disturbed by interrupts. exists 3 the vectors are reversed when a trapx instruction is executed coincident with an interrupt to a higher priority context. exists 4 when using the rdy_n signal to insert wait states (chip select timing register rdy_enable bit = 1), the address bus timing is incorrect. exists 5 when using a jmp or jsr instruction in pc indirect with base displacement addressing mode in assembly code projects , the cpu does not execute the instruction correctly. exists 12.2 detail errata no. 1 problem: adc start register bit 0 (start) does not self - clear when non - scanning mode conversion for single channel or multi - channel is selected. description: scanning mode is controll ed by adc control register bit 6 (scan). flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 69 of 74 1 - 888 - 824 - 4184 adc control register bit 4 (cd - conversion done) will correctly indicate that conversion(s) are done. an adc interrupt will be issued if adc interrupts are enabled. adc interrupts are enabled by setting adc control register bit 3 (irq_en) to 1. adc data available register will correctly indicate which channels have updated results in their data registers. workaround: when using non - scanning mode conversions , enable the adc between each commanded conversion (single channel or multi - channel): clear adc control register bit 7 (en) to 0 . set adc control register bit 7 (en) to 1 . set adc start register bit 0 (start) to 1 to start the conversion process . adc conversion complete will be indicated by: C an adc interrupt, if a dc control register bit 3 (irq_en) is set to 1 . C adc control register bit 4 (cd - conversion done) will set to i ndicate that conversion(s) are done. errata no. 2 problem: fatal fault recovery sequence can be disturbed by interrupts. description: context fa tal faults can occur if a context's stack pointer becomes corrupted. it is a feature of the hardware to detect this "fatal fault" and allow a graceful recovery by direct ing an exception to the master context. this operation can be disturbed if, by chance, an interrupt is triggered during a bus cycle leading to a fatal fault. this problem occurs no matter which context the interrupt is directed to. it need not be the faulting context. furthermore, since neither interrupt timing nor fatal faults are predictab le, there is no way to guarantee this cannot happen. the effect of this error depends on the interrupt mode of the context to which the interrupt is directed. if the interrupted context is running in fast single threaded mode, when an interrupt targeted to it occurs during a faulting bus cycle (caused by another context) the cpu will lock up after the faulting bus cycle completes. if the interrupted context is in standard or fast vectored mode the cpu will not lock up but the normal fault handling process w ill be disrupted. the effect is: both the interrupted and the faulting context will be set to halted. the fatal fault exception will be directed to the interrupted context rather than the master. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 70 of 74 1 - 888 - 824 - 4184 the expected interrupt will be directed (queued behind the fatal fault exception) to the interrupted context. the master context will be moved to the ready state, with no modification of its program counter, thus it will start running from where it left off previously. all other contexts are unaffected. errata no . 3 problem: the vectors are reversed when a trapx instruction is executed coincident with an interrupt to a higher priority context. description : given a low priority context currently executing and the master context and a higher priority context slee ping, if an interrupt comes in for the higher priority context simultaneously with the execution of a trapx instruction in the low priority context, it can happen that the interrupt handler is executed by the master context (even though intended for the hi gher priority context), while the trapx handler is executed by the higher priority context. workaround: the workaround involves several issues: 1. any interrupt handlers intended for other than the lowest priority context should be executable by the maste r context. 2. the master context must have a valid vector to the appropriate interrupt handlers. either the master context and the other contexts share a vector table or the vectors are duplicated on the master context's table. if the master context is execut ed in a different mode than the other contexts (e.g. master in standard mode, other context in fast - vectored mode), then a second interrupt handler must be coded that is compatible with the master context's operating mode. 3. trapx handlers should verify that they are being executed in the master context . t his assumes that they are performing some action that can only be executed in the master context, and if so , then they should execute and set a flag to alert the caller that they executed . i f not , then they should return without setting the flag. also, trapx handlers must be present (in the appropriate execution mode) on all vector tables. 4. the routine executing a trapx instruction should check the handshake flag from the trapx handler after execution of the i nstruction . i f it is not set appropriately, the trapx should be executed again. the approach given in 3 and 4 above, while more complex than simply having the trapx handler issue a trapx instruction if not executed in the master context, avoids the issue of flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 71 of 74 1 - 888 - 824 - 4184 trapx handlers that rely on the faulted context register to determine what specific action to take. errata no. 4 problem: when using the rdy_n signal to insert wait states (chip select timing register rdy_enable bit = 1) , the address bus timing is inc orrect. description: when used in this way , the address bus will change states coincident with, or in some cases, before the end of the bus cycle. this can cause data corruption in memory. workaround: there is no work around for this problem. it is recom mended to avoid use of the rdy_n signal and the rdy_enable bit of the chip select timing registers. errata no. 5 problem : when using a jmp or jsr instruction in pc indirect with base displacement addressing mode in assembly code projects , the cpu does no t execute the instruction correctly. description : instead of jumping indirectly to the location pointed to by the effective address, execution jumps to the effective address directly. workaround : there is no workaround for this problem. for assembly code projects, avoiding use of the pc indirect addressing with base displacement mode is recommended. flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 72 of 74 1 - 888 - 824 - 4184 13. revision history table 2 4 presents the sequence of revisions to document ia 211080807 . table 24 . revision history date revision descr iption page(s) august 8, 2007 00 first edition released . na september 11 , 2008 0 1 reformatted to meet publication standards. technical data updated. errata added. na october 9, 2008 02 changed reset to reset_n and reset_out to reset_out_n in t ext, figures, and tables. 17, 19, 26, 28, 35, 37, 50, 51 in table 5, changed pin numbers in data row 14 from f3 to g3 and in data row 19 fro m g3 to h3. 36 in tabl e 5, changed pin numbers in data row 11 from m14 to m15 and in data row 14 from m15 to m14. 39 deleted last row of table 5 (duplicate) . 40 in table 7, changed numbers in data row 1 from m14 to m15 and in data row 2 from m15 to m14. 43 in table 10, changed numbers in data rows 13, 14, 15, and 16 to b6, p13, p14, and C , from p5, b6, p13, and p14 , respectively, for column labeled b ga 15 x 15 . 44 added 2 new sentences at beginning of section 7.2, signal considerations and reset timing. 50 changed clkvdd to vddclk and clkgnd to gndc lk in note and figures 11, 12, and 13. 52, 53 updated errata chapter to reflect errata for version 01. 76 through 8 7 october 10, 2008 03 to conform to publication standards, r emoved illustration from cover. changed table 24, part numbers by package types , to reflect version 01 part numbers . 1, 75 march 12, 2009 04 revised o rdering i nformation C package information; added errata 2. 75 - 78 july 28 , 2009 05 revised description of when bus cycle terminates in a read cycle ; added two errata. 61, 64 , 76, 78, 79 november 20, 2009 06 updated lpstop power consumption. 49 april 15 , 2010 07 added bga signal routing guidance. 43, 44 april 25, 2012 08 added errata 5 81 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 73 of 74 1 - 888 - 824 - 4184 date revision descr iption page(s) december 11, 2012 09 removed references to 10x10 bga package; added thermal characteri stics data. 10, 41 april 10, 2013 10 corrected o scillator s tartup time ( t st ) 39 flexible input deterministic output (fido ? ) data sheet 32 - bit real - time communications controller april 1 0 , 201 3 ia211080807 - 1 0 http://www.innovasic.c om uncontrolled when pr inted or copied customer support: page 74 of 74 1 - 888 - 824 - 4184 14. for additional information innovasics FIDO1100 is the first product in the fido family of real - time communication controller s. the fido communication controller architecture is uniquely optimized for solving memory bottlenecks, and i s designed from the ground up for deterministic processing. critical timing parameters, such as context switching and interrupt latency, are precisely predictable for real - time tasks. the FIDO1100 also incorporates the universal i/o controller (uic ) tha t is configurable to support various communication protocols across multiple platforms. this flexibility relieves the designer of the task of searching product matrices to find the set of peripherals that most closely match the system interface needs. th e s oftware p rofiling and i ntegrated d ebug e nvi r onment (spider ) has extensive real - time code debug capabilities without the burden of code instrumentation. the FIDO1100 user guide and the FIDO1100 instruction set reference guide as well as other helpful tools and files are available . for example, t he gdb debugger s upports both profiling and tracing of executing code. the innovasic support team is continually planning and creating tools for your use. visit http://www.innovasic.com for up - to - date documentation and software. our goal is to provide timely, complete, accurate, useful, and easy - to - understand information . please feel free to contact our experts at innovasic at any time with suggestions, comments, or questions. innovasic support team 5635 jefferson st. ne, suite a albuquerque, nm 87109 usa (505) 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 e - mail: support@innovasic.com website: http://www.innovasic.com |
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